Comprehensive Product Summary – ADLINK ACL‑8312/L AT‑Bus Data Acquisition Card

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### 1. Product Overview

Product Name: ACL‑8312/L
Model: ACL‑8312/L (Lite version of ACL‑8316/12 series)
Series: ACL‑8316/8312 High‑Performance DAS (Data Acquisition System) Cards
Article Number: ACL‑8312/L
Manufacturer: ADLINK Technology Inc.
Trademark: NuDAQ® (registered trademark of ADLINK Technology Inc.)
Product Type: AT‑Bus Analog‑to‑Digital (A/D) Data Acquisition Card
Form Factor: Half‑size ISA (PC/AT) card
Manufacturer Address: 9F, No. 166, Jian Yi Road, Chungho City, Taipei 235, Taiwan, R.O.C.
Website: [www.adlink.com.tw](http://www.adlink.com.tw)

The ACL‑8312/L is a high‑performance, 12‑bit analog input data acquisition card designed for PC/AT systems using the ISA bus. It is part of ADLINK’s NuDAQ family of multifunction DAS cards, offering high‑speed sampling, programmable gain, and integrated digital I/O and timing functions. The “L” (Lite) version omits analog output channels for cost‑sensitive applications that require only A/D conversion and digital I/O.

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### 2. Key Features

- High‑Speed A/D Conversion:
12‑bit resolution with up to 100 kS/s sampling rate using a Burr‑Brown ADS7804 or equivalent successive‑approximation ADC.

- Channel Configuration:
16 single‑ended (SE) or 8 differential (DI) analog input channels, selectable via jumper (JP7).

- On‑Board FIFO Buffer:
1K‑word FIFO memory for continuous, gap‑free data acquisition with half‑full and full interrupt flags.

- Programmable Gain Amplifier:
Software‑selectable gains of ×1, ×2, ×4, ×8 for input ranges of ±10 V, ±5 V, ±2.5 V, ±1.25 V.

- Triggering Flexibility:
Supports software, internal pacer (timer‑based), and external trigger modes for A/D conversion.

- Data Transfer Options:
Software polling, interrupt‑driven, FIFO polling, FIFO half‑full interrupt, or DMA (Direct Memory Access) transfer.

- Digital I/O:
16 TTL‑compatible digital input and 16 TTL‑compatible digital output channels.

- Timer/Counter:
Three independent 16‑bit programmable down counters (Intel 8254 compatible) with a 2 MHz base clock; two cascaded for A/D pacer timing, one user‑programmable.

- Interrupt and DMA Support:
Selectable IRQ levels (3, 5–7, 9, 11, 12, 15) and DMA channels (5, 6, 7).

- Power and Stability:
On‑board DC/DC converter for stable analog power isolation from digital noise.

- Compact Design:
Half‑size ISA card (163 mm × 123 mm) with 37‑pin D‑type and dual 20‑pin IDC connectors.

- Software Support:
Includes DOS C/C++ library, Windows DLL (ACLS‑DLL2), and LabVIEW driver (ACLS‑LVIEW).

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### 3. Technical Specifications

Analog Input (A/D):
- Converter: Burr‑Brown ADS7804 or equivalent
- Resolution: 12 bits
- Channels: 16 SE or 8 DI
- Conversion Time: 8 µs
- Max Sampling Rate: 100 kS/s (multiplexed)
- Input Ranges (programmable): ±10 V, ±5 V, ±2.5 V, ±1.25 V
- Input Type: Bipolar, programmable gain ×1/×2/×4/×8
- Input Impedance: 10 MΩ
- Over‑voltage Protection: ±35 V continuous
- Accuracy:
- Gain 1: 0.01% FSR ±1 LSB
- Gain 2,4: 0.02% FSR ±1 LSB
- Gain 8: 0.04% FSR ±1 LSB
- Data Format: Two’s complement
- FIFO Buffer: 1K words with half/full interrupt
- Trigger Modes: Software, internal pacer, external pulse
- Data Transfer: Polling, interrupt, FIFO, DMA

Digital I/O:
- Channels: 16 input + 16 output (TTL/DTL compatible)
- Input Voltage:
- Low ≤ 0.8 V
- High ≥ 2.0 V
- Output Voltage:
- Low ≤ 0.4 V @ 8 mA sink
- High ≥ 2.4 V @ 0.4 mA source
- Input Load: 0.2 mA max
- Output Drive: 8 mA sink, 0.4 mA source

Timer/Counter (8254 compatible):
- Counters: 3 × 16‑bit down counters
- Base Clock: 2 MHz
- Pacer Output Range: 0.00046 Hz to 100 kHz
- Modes: 0–5 (Interrupt on terminal count, one‑shot, rate generator, square wave, software/hardware strobe)
- Counter 0: User programmable
- Counters 1 & 2: Cascaded for A/D pacer

General:
- Bus Interface: 16‑bit ISA (AT)
- I/O Base Address: 16 consecutive addresses (default 0x220)
- IRQ Levels: 3, 5, 6, 7, 9, 11, 12, 15
- DMA Channels: 5, 6, 7
- Connectors:
- CN1: 20‑pin digital output
- CN2: 20‑pin digital input
- CN3: 37‑pin D‑type analog I/O and timer signals
- Power Requirements: +5 V @ 400 mA, +12 V @ 260 mA (typical)
- Dimensions: 163 mm (L) × 123 mm (H)
- Operating Temperature: 0–55 °C
- Storage Temperature: –20–80 °C
- Humidity: 5–95% non‑condensing

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### 4. Functionality

Operation Principle:
The ACL‑8312/L performs analog‑to‑digital conversion using a successive‑approximation ADC. Input signals are multiplexed across 16 SE or 8 DI channels, amplified by a programmable gain amplifier, and digitized into 12‑bit two’s‑complement data. The onboard FIFO buffer allows continuous sampling without CPU intervention. Data can be transferred via software polling, interrupt, or DMA.

Use Cases and Applications:
- Industrial process monitoring and control
- Laboratory data logging and signal analysis
- Energy management and automation systems
- ON/OFF control and annunciation
- Security and alarm systems
- Product testing and quality assurance
- Period and pulse‑width measurement

Compatibility:
- PC/AT ISA bus systems
- Supported OS: DOS, Windows 3.1/95/98/NT
- Software Environments: C/C++, Visual C++, Visual Basic, Delphi, LabVIEW

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### 5. Components & Accessories

Included Items:
- ACL‑8312/L data acquisition card
- ADLINK CD (drivers, utilities, manuals)
- User’s Guide

Optional Daughter Boards:
- ACLD‑8125: 37‑pin D‑sub terminal board with cold‑junction compensation (for thermocouples).
- ACLD‑9137: Direct 37‑pin connector board for simple analog signal wiring.
- ACLD‑9182: 16‑channel isolated digital input board (500 VDC isolation).
- ACLD‑9185: 16‑channel SPDT relay output board for external device control.
- ACLD‑9188 / ACLD‑9138: General‑purpose terminal boards (barrier‑strip or screw‑clamp).

Connectors:
- CN1 (20‑pin): Digital Output (DO0–DO15)
- CN2 (20‑pin): Digital Input (DI0–DI15)
- CN3 (37‑pin D‑type): Analog Inputs (AI0–AI15), Timer/Counter, External Trigger, Analog Ground, +5 V, +12 V

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### 6. Installation & Setup

System Requirements:
- IBM‑compatible PC with available 16‑bit ISA slot
- DOS or Windows 95/98/NT environment
- Proper IRQ and DMA resource availability

Installation Steps:
1. Use anti‑static precautions during unpacking.
2. Insert the card into an ISA slot.
3. Configure base I/O address (default 0x220) via DIP switch SW1.
4. Set jumpers for:
- Analog input mode (JP7: SE/DI)
- DMA channel (JP1, JP2: 5/6/7)
- IRQ level (JP3: 3,5–7,9,11,12,15)
- Timer clock source (JP4: internal 2 MHz or external CN3 pin‑37)
5. Connect external signals via CN1–CN3.
6. Install software drivers and utilities from the ADLINK CD.

Configuration Utilities:
- DOS utility `8316UTIL.EXE` for system configuration, calibration, and functional testing.
- Windows DLL and LabVIEW drivers for high‑level programming.

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### 7. Performance & Capabilities

Sampling Performance:
- 100 kS/s maximum throughput (multiplexed)
- 8 µs conversion time per channel
- 1K FIFO buffer for continuous acquisition

Resolution & Accuracy:
- 12‑bit resolution (1 part in 4096)
- ±0.01–0.04% FSR accuracy depending on gain

Data Transfer Efficiency:
- DMA transfer for high‑speed, CPU‑independent operation
- Interrupt‑driven FIFO half‑full mode for real‑time Windows applications
- Software polling for low‑speed or simple tasks

Timing & Synchronization:
- Internal pacer timer (2 MHz base) for precise sampling intervals
- External trigger input for event‑driven acquisition
- Programmable counter for user timing or event counting

Limitations:
- ISA bus interface (legacy systems only)
- No analog output channels (Lite version)
- Maximum sampling rate limited by ADC conversion time and bus bandwidth

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### 8. Standards & Compliance

- Bus Interface: 16‑bit ISA (AT)
- Digital Logic Levels: TTL/DTL compatible
- Timer/Counter: Intel 8254 compatible
- DMA Controller: 8237 compatible
- Interrupts: PC standard IRQ lines
- Environmental Compliance: Operating 0–55 °C, 5–95% RH non‑condensing
- Electrical Safety: ±35 V over‑voltage protection on analog inputs
- Software Standards: Compatible with ADLINK NuDAQ driver architecture (ACLS‑DLL2, ACLS‑LVIEW)

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### 9. Additional Information

Calibration:
- On‑board variable resistors (VR1–VR7) for fine adjustment:
- VR1: A/D offset
- VR2: A/D full‑scale
- VR7: A/D amplifier offset
- Calibration procedure supported by software utility and external DVM.

Maintenance:
- Periodic calibration recommended for accuracy.
- Avoid exposure to excessive heat, humidity, or static discharge.

Warranty:
- One‑year limited warranty from date of purchase.
- Covers defects in materials and workmanship.
- Excludes damage from misuse, modification, or operation beyond specifications.
- Return shipping prepaid; proof of purchase required.

Technical Support:
- Sales & Service: service@adlink.com.tw
- Technical Support: nudaq@adlink.com.tw
- Phone: +886‑2‑82265877
- Fax: +886‑2‑82265717

Software Updates:
- ADLINK provides updated drivers and libraries via official website and support channels.
- Supported development environments: Borland C/C++, Microsoft Visual C++, Visual Basic, Delphi, LabVIEW.

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### Summary

The ADLINK ACL‑8312/L is a robust, high‑speed, 12‑bit data acquisition card for ISA‑bus PCs, optimized for industrial and laboratory measurement applications. It combines flexible analog input configuration, programmable gain, and integrated digital I/O and timing functions. With its 1K FIFO buffer, DMA support, and multiple trigger modes, it ensures reliable, continuous data capture at up to 100 kS/s. The card’s modular design allows expansion via optional daughter boards for isolated I/O or relay control. Supported by comprehensive software libraries and calibration utilities, the ACL‑8312/L delivers precise, stable, and efficient data acquisition performance for legacy PC‑based control and monitoring systems.